1. Field
The present disclosure generally relates to the design of chip packages. More specifically, the present disclosure relates to a chip package that includes: a group of semiconductor dies arranged in a plank stack, an interposer plate oriented approximately at a right angle relative to the plank stack, and associated alignment features.
2. Related Art
The ability to provide low-latency and high-bandwidth access between a processor and memory remains a significant challenge in computer systems. To achieve the former, system designers are using packaging innovations to reduce the electrical path length between the processor and memory. For example, the processor and memory are now often implemented on a common package or interposer (as opposed to conventional individually packaged chips that are connected to a printed circuit board). Researchers are also attempting to stack memory chips directly onto a processor die. Moreover, in order to obtain a higher memory density per unit volume, several memory manufacturers are attempting to stack memory chips in the third dimension.
Chip packages that include stacked semiconductor chips can provide significantly higher performance in comparison to existing computer systems. These chip packages also provide certain advantages, such as the ability: to use different processes to fabricate different chips in the stack, to combine higher density logic and memory, and to transfer data using less power. For example, a stack of chips that implements a dynamic random-access memory (DRAM) can use a high metal-layer-count, high-performance logic process in a base chip to implement input/output (I/O) and controller functions, and a set of lower metal-layer-count, DRAM-specialized process chips can be used for the rest of the stack. In this way, the combined set of chips may have better performance and lower cost than: a single chip that includes the I/O and controller functions manufactured using the DRAM process; a single chip that includes memory circuits manufactured using a logic process; or a system constructed by attempting to use a single process to make both logic and memory physical structures.
However, integrating even one memory chip onto a processor or an application-specific integrated circuit (ASIC) can be difficult. Typically, face-to-face integration is not used because this configuration can block access to power/ground and signal I/O lines for the processor. On the other hand, stacking the memory chip(s) on the back face of the processor typically involves the use of through-silicon-vias (TSVs) in the processor. In a TSV fabrication technique, chips are processed so that one or more of the metal layers on their active face are conductively connected to new pads on their back face. Then, chips are adhesively connected in a stack, so that the new pads on the back face of one chip make conductive contact with corresponding pads on the active face of an adjacent chip.
TSVs are typically more expensive than existing interconnect techniques (such as wire bonds), because TSVs pass through the active silicon layer of a chip. As a consequence, a TSV occupies area that could have been used for transistors or wiring. This opportunity cost can be large. For example, if the TSV exclusion or keep-out diameter is 20 μm, and TSVs are placed on a 30-μm pitch, then approximately 45% of the silicon area is consumed by the TSVs. This roughly doubles the cost per area for any circuits in the chips in the stack. (In fact, the overhead is likely to be even larger because circuits are typically spread out to accommodate TSVs, which wastes more area.) Furthermore, fabricating TSVs usually entails additional processing operations and yield loss, which also increase cost. In addition, TSVs occupy the surface traditionally used for cooling, which usually presents a significant challenge for thermal management, and thus often limits the number of stacked semiconductor dies.
Hence, what is needed is a chip package that offers the advantages of stacked semiconductor dies without the problems described above.